LPC Verification IP
Truechip's LPC Verification IP provides an effective & efficient way to verify the LPC components of an IP or SoC. Truechip's LPC VIP is fully compliant with LPC Specification version 1.1 The VIP is lightweight with easy plug-and-play components so that there is no hit on the design cycle time.
Key Benefits
- Available in native SystemVerilog (UVM/OVM/VMM) and Verilog.
- Unique development methodology to ensure the highest levels of quality.
- Availability of various Regression Test Suites.
- 24X5 customer support
- Unique and customizable licensing models
- Exhaustive set of assertions and cover points with connectivity examples for all the components.
- Consistency of interface, installation, operation, and documentation across all our VIPs.
- Provide complete solutions and easy integration in IP and SoC environments.
Features
- Compliant with LPC 1.1 specifications
- Supports the following operations
- Memory Read and Write
- Bus Master Memory Read and Write
- I/O Read and Write
- Bus Master I/O Read and Write
- Firmware Memory Write and Read
- DMA read and write
- Supports bandwidth up to 33Mhz
- Host and Device support all LPC transactions
- Supports Power State transaction
- Supports Wake up transaction
- Supports LDRQ and Sync Rules
- Support for interrupts
- Support for wait states
- Callbacks for error injections
- Monitors, detects and notifies the testbench of significant events such as transactions, warnings, timing, and protocol violations.
- In-built coverage analysis
- LPC VIP comes with a complete test suite to verify every feature
- LPC VIP comes with a Transaction analyzer and Performance Monitors
Deliverables
